The present disclosure relates to semiconductor memory devices, and more particularly, to semiconductor memory devices in which accurate sense amplifier activation timing is generated using dummy memory cells.
Conventionally, for static random access memory (SRAM), there is a known technique of generating the timing of activating sense amplifiers using data read from a plurality of dummy memory cells each having the same transistor characteristics as those of memory cells. By the technique, the memory device can be accurately read without an influence of process variations and changes in ambient temperature or power supply voltage (see K. Osada et al., “Universal-Vdd 0.65-2.0-V 32-kB Cache Using a Voltage-Adapted Timing-Generation Scheme and a Lithographically Symmetrical Cell,” IEEE Journal of Solid-State Circuits, Vol. 36, No. 11, pp. 1738-1744, November 2001).
There is also a proposed technique of generating the timing of activating sense amplifiers using dummy memory cells, taking into consideration the load of a column selector connected to bit lines of memory cells or a delay caused by the resistance of the bit line (see Japanese Patent Publication No. 2004-171633).
Here, a problem with the conventional technique of reducing the read time will be described. As device miniaturization by microfabrication process is advanced by scaling, variations in shape or amount of implanted impurity tend to increase, and therefore, variations in transistor characteristics tend to increase. In particular, the influence of the increase of the variations is obviously large on extremely small transistors used, for example, in memory cells. In the conventional art, variations in transistor characteristics can be reduced by using a plurality of dummy memory cells in a read circuit including dummy memory cells. In a single-end type amplifier which uses an inverter to read a dummy memory cell, in order to generate the timing of activating a cross-coupled type sense amplifier which amplifies complimentary data to read a memory cell, the potential difference of the complimentary data read from the memory cell needs to be sufficiently large for amplification of the memory cell sense amplifier when the inverter for the dummy memory cell activates an activation timing signal to a level exceeding the switching level. In order to accurately generate the timing, for example, it is necessary to reduce variations in the switching level of the inverter, or to adjust the read capability of the dummy memory cell so that the time required for the inverter to reach the switching level is equal to the time required to generate a potential difference required for amplification of the sense amplifier, i.e., considerably difficult circuit tuning is required. In other words, because the dummy memory cell is used, variations in transistor characteristics caused by the influence of the fabrication process etc. can be beneficially followed to obtain similar operation, and therefore, the use of the dummy memory cell is suitable for generation of the timing of activating the sense amplifier which is sufficient to prevent a failure in reading of memory cell data. However, it is difficult to reduce the read time.
Next, a technique of generating timing by using a delay of an inverter having logic transistor characteristics without using the dummy memory cell will be described. It is relatively easy to activate a sense amplifier activation timing signal by adjusting the drive capability of the inverter delay or the number of stages of delay circuits at a timing when the potential difference of complimentary data becomes one that is required for amplification of a sense amplifier, in order to generate the timing of activating the sense amplifier by using an inverter delay circuit including logic transistors. Because logic transistors are used as the inverter delay circuit, the area efficiency is considerably high compared to a read circuit which uses dummy memory cells corresponding to a column of memory cells, and variations in transistor characteristics can be reduced by increasing the transistor capability of the inverter delay circuit to some extent. However, the process variations, particularly, variations of the logic transistors and the memory cell transistors having different amounts of implanted impurity, may not have the same behavior. In particular, the difference in characteristics becomes significant, for example, under conditions that the power supply voltage is low or that the temperature is high or low. Even if timing is generated without a problem under normal conditions, the characteristics of the memory cell transistors may become extremely worse than the characteristics of the logic transistors under the above corner conditions, and the memory cell read operation may be excessively delayed from the timing of activation of the sense amplifier, resulting in erroneous operation.